1. Field of the Invention
The present invention relates to a method and an apparatus for generating a layout pattern of a semiconductor device (a basic cell), for use in designing a layout of a semiconductor integrated circuit.
2. Description of the Related Art
A variety of layout design methods, i.e., a variety of layout drawing methods using a layout drawing apparatus, have been proposed for use in designing a layout of a semiconductor integrated circuit. See the Japanese Patent Application Kokai (Laid-Open) Publication No. 8-96002 (patent document 1), the Japanese Patent Application Kokai (Laid-Open) Publication No. 2000-195958 (patent document 2), and the Japanese Patent Application Kokai (Laid-Open) Publication No. 2003-36280 (patent document 3), for instance.
Representative examples are methods 1 to 3 given below.
Method 1: All layout patterns that would be needed in the layout design phase are drawn in advance and stored. These layout patterns are used to design a layout of a semiconductor integrated circuit.
Method 2: Basic layout patterns are drawn in advance and stored. In the layout design phase, a size of the basic layout pattern is changed to create a desired layout pattern, and the desired layout pattern is used to design a layout of a semiconductor integrated circuit.
Method 3: Basic layout patterns are drawn in advance and stored. Size-changeable items of the basic layout patterns are specified as parameters. In the layout design phase, the parameter value is specified to change a size of the basic layout pattern to create a desired layout pattern. The desired layout pattern is used to design the layout of a semiconductor integrated circuit.
The method 1 described above requires humans to draw all the layout patterns that would be needed, by using a drawing apparatus. Since a great number of layout patterns must be drawn, there is a high probability that a drawing error is included in the layout patterns.
The methods 2 and 3 require humans to draw a basic layout pattern beforehand by using a drawing apparatus and also require manual input of a parameter value for changing a size of the basic layout pattern. There is a probability of a basic layout pattern drawing error or a parameter value input error, causing an error to be included in a layout pattern generated on the basis of the basic layout pattern.
The layout patterns used in the phase of designing the layout of a semiconductor integrated circuit depend on the process technology used in the fabrication of the semiconductor integrated circuit. Accordingly, the method 1 described above requires the layout patterns to be drawn and stored for each process technology, and the methods 2 and 3 described above require basic layout patterns to be drawn and stored for each process technology. In both cases, a large number of layout patterns must be drawn beforehand, and the work requires much effort and time.
In addition, since the layout patterns used in designing the layout of a semiconductor integrated circuit depend on the process technology for use in fabricating the semiconductor integrated circuit, a change in the process technology requires humans to change the layout patterns by using a drawing apparatus in the method 1 described above. In the methods 2 and 3 described above, humans must change the basic layout patterns and desired layout patterns generated on the basis of the basic layout patterns by using a drawing apparatus. Each time the process technology is changed, much effort and time must be expended in any method.